1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, more particularly, to a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy.
2. Description of the Related Art
The inventors of the present invention developed an analog and many-valued semiconductor memory device utilizing a MOS transistor with a floating gate (Japanese Patent Application No. Hei 9-24063).
After carrying out the study in order to improve the semiconductor memory device and achieve higher integration and quick, accurate writing and reading characteristics, we found that the semiconductor memory device included some following problems. The present invention has been completed according to such teachings as:
(1) A voltage used when data are written into a memory cell, for example, a high voltage applied to a tunnel oxide film when data are written into a tunnel oxide film by flowing a Fowler-Nordheim current therethrough, uses a predetermined constant voltage independent of values which are desired to be stored in the memory cell, so that there is a limit to write data into the memory cell at high speed and with high precision.
(2) When an offset voltage that occurs in a memory cell is corrected, an offset voltage of a dummy cell different from the memory cell into which data are written is detected, and by using the voltage value detected, the correction of the offset voltage of the memory cell into which data are written is performed. Accordingly, when there is any difference in manufacture between the memory cell for writing and the dummy memory cell, the effect of correction of the offset voltage is faded out, thereby causing highly accurate writing operation to be impossible.
(3) Control for correcting an offset voltage occurring in a memory cell is complicated, and also all of the voltage ranges readable from a circuit which reads out values stored in the memory cell can not be used as a range of voltage values for storing in the memory cell.
(4) Two transistors are used as a configuration of a memory cell, so that the occupied area of a memory cell on a chip becomes large, preventing high integration.
The present invention has been made in view of the above-described background, and therefore, is intended to provide a semiconductor circuit which can store analog and many-valued data quickly and accurately and further, which can be highly integrated.
The first semiconductor memory device according to the present invention comprises a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, a write voltage controlling circuit having an output terminal which outputs an output voltage corresponding to the analog and many-valued voltage values inputted to an input terminal as a writing voltage of the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator.
A writing operation is performed by producing a writing voltage corresponding to a value which is stored in the memory cell as the voltage used for writing the value to the memory cell and by supplying the writing voltage to the memory cell. As a result, the time from starting the writing operation in the memory cell to stopping the operation is substantially constant, independent of a value to be stored, thereby allowing high speed and high precision writing.
The second semiconductor memory device according to the present invention comprises a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparison calculation circuit having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals a predetermined voltage, a comparator having a means for inputting a voltage produced by adding a difference of the readout voltage of the output terminal and a standard voltage to a write target voltage to the predetermined voltage of the comparison calculation circuit, a write voltage controlling circuit having an output terminal which outputs a voltage for writing in the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator, and
wherein writing activity is performed by executing a first writing in the memory cell by inputting the standard voltage to the predetermined voltage, and by inputting the voltage obtained by adding the difference of the readout voltage outputted on the output terminal of the readout circuit and the standard voltage to the write target voltage to the predetermined voltage of the comparison calculation circuit, immediately after the end of the first writing, as a second writing to the memory cell to which the first writing has been performed.
In this way, when an offset voltage of a memory cell is corrected, the offset voltage is detected by performing preliminary writing to the cell to be written, and by using the detected value, the offset voltage is corrected. As a result, when data are written to the memory cell, errors due to manufacturing difference can be eliminated, allowing writing activity to perform with high precision.
The third semiconductor memory device according to the present invention includes two or more memory devices, one of which comprises a floating gate in which analog and many-valued signals can be written and stored and further the analog and many-valued signals can be stored as an amount of charges, a memory cell having a control gate which performs capacitive coupling with the floating gate, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, and a write voltage controlling circuit having an output terminal which outputs a voltage for writing in the memory cell and a means for outputting, and also including a function which stops to supply the voltage for writing of the output terminal to the memory cell when the write end signal is outputted to the output terminal of the comparator,
and further, comprises a differential amplifier which includes a plus input terminal and a minus input terminal and amplifies the difference of voltage values of the plus input terminal and the minus input terminal to output as a voltage, and a control gate controlling circuit which is provided with a means for connecting the output of the differential amplifier to both of the control gates of a first memory device and a second memory device, and
wherein writing to the first memory device is performed by inputting a standard voltage to the predetermined voltage of the first memory device and by setting the control gate of the memory cell of the first memory device to a reference voltage, writing to the second memory device is executed by causing the control gate of the memory cell of the second memory device to be a reference voltage and by inputting a write target voltage to the predetermined voltage, and when the value stored in the memory cell of the second memory device is read out, the readout activity is performed with high precision by connecting an output of the output terminal of the readout circuit of the first memory device to the minus terminal of the differential amplifier, by connecting the standard voltage to the plus terminal of the differential amplifier, and by connecting the output of the differential amplifier to the control gates of the first and second memory devices.
In addition, the fourth semiconductor memory device according to the present invention includes two or more memory devices comprising a floating gate in which analog and many-valued signals can be written and stored and further the analog and many-valued signals can be stored as an amount of charges, a memory cell having a control gate which perform capacitive coupling with the floating gate, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, and a write voltage controlling circuit having an output terminal which outputs voltage for writing in the memory cell and a means for outputting, and also including a function which stops to supply the voltage for writing of the output terminal to the memory cell when the write end signal is outputted to the output terminal of the comparator,
and further, comprises a differential amplifier which includes a plus input terminal and a minus input terminal and amplifies the difference of voltage values of the plus input terminal and the minus input terminal to output as a voltage, and a control gate controlling circuit which is provided with a means for connecting the output of the differential amplifier to both of the control gates of a first memory device and a second memory device, and
wherein, after writing to the first memory device has been performed by inputting a standard voltage to the predetermined voltage of the first memory device to cause the control gate of the memory cell of the first memory device to be a reference voltage, writing activity is performed by connecting an output of the output terminal of the readout circuit of the first memory device to the minus terminal of the differential amplifier, by connecting the standard voltage to the plus terminal of the differential amplifier, by connecting the output of the differential amplifier to the control gates of the first and second memory devices, and by inputting a write target voltage to the predetermined voltage of the second memory device.
As described above, the third and fourth semiconductor memory devices according to the present invention correct the offset voltage of the memory cell by controlling the voltage of the control gate of the memory cell. As a result, writing control is simple, and also the voltage range readable from the readout circuit can be used as it is as a write target value.
The fifth semiconductor memory device according to the present invention, in a semiconductor memory device which has a plurality of memory cells including MOS transistors with floating gates, control gates performing first capacitive coupling with the floating gates, and write terminals performing second capacitive coupling with the floating gates and capable of writing and storing analog and many-valued signals, and has a readout circuit capable of writing to a selected memory cell and outputting a voltage of the floating gate of the selected memory cell to the output terminal,
is characterized in that selection of the memory cell is performed by voltage control of the control gate, and in writing activity to the memory cell, the voltage of the floating gate is outputted to the output terminal using the readout circuit simultaneous with writing, and termination judgment for writing is executed based on the output voltage of the output terminal to terminate the writing activity.
The selection of a cell for writing and reading is not performed, as with the prior art, by providing with a MOS transistor and controlling the transistor, but performed by controlling the voltage of the control gate. Consequently, the MOS transistor to select a memory cell can be eliminated and the memory cell can be constituted by one MOS transistor, allowing the memory cell to be highly integrated.